1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device with a multi-layered storage node and a method for fabricating the same.
2. Description of the Related Art
In a DRAM, a capacitance (Cs) of a capacitor, e.g., a capacitor formed by using under-30 nm process, decreases with reduction in a pitch size. Accordingly, in order to increase the capacitance, open parts with a high aspect ratio, e.g., an aspect ratio of 30 or over, are formed and an etching process for forming the open parts is to be used in a DRAM fabrication process. The open parts are obtained by etching a mold layer, and storage nodes are formed in the open parts. As the height of the storage nodes increases, a high aspect ratio etching process is to be used. Since the high aspect ratio etching process is difficult to perform, a method of stacking storage nodes into at least two layers has been proposed. For example, a generally known method for forming storage nodes into double layers may be performed in the sequence of forming a first mold layer, forming first open parts, forming first storage nodes, forming a second mold layer, forming second open parts and forming second storage nodes.
Such a method for forming storage nodes into at least two layers is a costly process with a markedly increased number of processing steps.
Furthermore, as the height of storage nodes increases, the height of a mold layer increases as well. Thus, the layer of metal contacts (M1C) is heightened. Here, the metal contacts (M1C) refer to contacts for connecting metal lines (M1) with plates of capacitors. Also, the metal contacts refer to contacts for the metal lines (M1) which are connected to bit lines with sources/drains of transistors of a peripheral circuit region.
In the case where the height of a mold layer is increased to secure the capacitance of capacitors, an aspect ratio increases as the depth of contact holes for metal contacts formed in the peripheral circuit region increases. Due to this fact, contact holes may not be open during an etching process or a bottom critical dimension decreases even when the contact holes are open, which leads to poor filling of metal contacts in the contact holes.